RMC150 Register Map - File 144-149 Slot Settings

RMC150 Registers, File 144-149: Slot Settings

These registers control the settings for the module in each slot.

Tip:
For the DF1/CSP addressing format, all 'F' type registers (32-bit floating point) can also be read as 'L' type (32-bit word) registers. This is very useful when reading registers with DWORD or DINT external data types.

Modules RMC150E, RMC151E, M, S, Q, A, G, H, DI/O

Slot n = 0-5

DF1,CSP
Address

Modbus
TCP,RTU
Address

FINS

Address

External

Data Type

Internal

IEC
Address

Internal
Data Type

Access

F144+n:0

73729
+512 x n

E1_08192
+512 x n

DINT

%MD144+n.0

DINT

Read Only

Slot n Module ID

F144+n:1

73731
+512 x n

E1_08194
+512 x n

DWORD

%MD144+n.1

DWORD

Read Only

Slot n Module Rev

Module UI/O

Slot n = 0-5

AB DF1,CSP Address	Modbus TCP,RTU Address	FINS Address	External Data Type	Internal IEC Address	Internal Data Type	Access	Register Name
F144+n:0	73729 +512 x n	E1_08192 +512 x n	DINT	%MD144+n.0	DINT	Read Only	Slot n Module ID Module ID = 45 (comm slot) Module ID = 77 (sensor slot)
F144+n:1	73731 +512 x n	E1_08194 +512 x n	DWORD	%MD144+n.1	DWORD	Read Only	Slot n Module Rev Major * 256 + Minor
F144+n:2	73733 +512 x n	E1_08196 +512 x n	DWORD	%MD144+n.2	DWORD	Read Only	Board Revision 0x00MMmmLL, where MM is major, mm is minor, and LL is letter (00=A, 01=B, etc.)
F144+n:3	73735 +512 x n	E1_08198 +512 x n	DINT	%MD144+n.3	DINT	Read Only	Serial Number Last 6 digits of the serial number (yyqnnn)
F144+n:4	73737 +512 x n	E1_08200 +512 x n	DWORD	%MD144+n.4	DWORD	Read Only	FPGA Image Date/Time Bits 20-31: Year (4-digit year) Bits 16-19: Month (1=Jan, etc.) Bits 11-15: Day (1..31) Bits 6-10: Hour (0..23, 0=12am, 1=1am, etc.) Bits 0-5: Minute (00-59)
F144+n:16	73739 +512 x n	E1_08202 +512 x n	DWORD	%MD144+n.16	DWORD	Read/Write	Channel 0 Mode Bits 0-3 - Channel Mode 0 = Quadrature Axis Input 1 = SSI Axis Input 2 = SSI Register Input 3 = SSI Output Bit 4 - SSI Master/Slave [Applies only to SSI Output and SSI Register Input modes] 0 = Master - Clock is an output 1 = Slave - Clock is an input
F144+n:17	73741 +512 x n	E1_08204 +512 x n	DWORD	%MD144+n.17	DWORD	Read/Write	Channel 0 SSI Options Applies only to SSI Output and SSI Register Input modes] Bit 0-5 - SSI Data Bits Range: 8-32 Bit 6 - SSI Encoding 0=Binary, 1=Gray Code Bit 8 - Terminate Inputs [Applies to all SSI Output and SSI Register Input modes except SSI Output - Master.] SSI Register Input - Standard: Data Inputs SSI Register Input - Monitor: Clock/Data Inputs SSI Output - Slave: Clock Inputs Bit 16-31 - SSI Clock Rate (kHz) Specifies the clock rate in kHz. The actual rate will be determined by the available integer divisor (16500/SSIClockRatekHz-1). Initial supported values are 250, 500, and 971, with the default of 250 kHz.
F144+n:18	73743 +512 x n	E1_08206 +512 x n	DINT	%MD144+n.18	DINT	Read/Write	Channel 0 Wire Delay [Applies only to SSI Register Input modes] Time to delay (ns) from Clock to Data. This value will be converted to the nearest time delay that can be represented with [1..8] * [0..31] / 33MHz.
F144+n:19	73745 +512 x n	E1_08208 +512 x n	DWORD	%MD144+n.19	DWORD	Read/Write	Channel 0 Source/Dest [Applies only to SSI Output and SSI Register Input modes] For SSI Output mode, this is the address of the register to send out the SSI Output. Ignored if Echo is enabled. For SSI Register Input, this is the address of the register to save the value coming in on the SSI input.
F144+n:20	73747 +512 x n	E1_08210 +512 x n	DWORD	%MD144+n.20	DWORD	Read Only	Channel 0 SSI Status [Applies only to SSI Output and SSI Register Input modes] Bit 0 - Clock Wire Fault Wire Break for Clock inputs, Short for Clock outputs. Bit 1 - Data Wire Fault Wire Break for Data inputs, Short for Data outputs. Bit 2 - No Master Detected - Two or more loops (SSI Slave modes only) No master device is clocking SSI data--two or more loops in a row. Bit 3 - No Slave Detected (SSI Register Input only) Transducer or RMC not responding with data. Bit 4 - No Master Detected - One or more loops (SSI Slave modes only) This status register indicates that no clocked data was detected this loop time, even if this is the first loop this occurred. Notice that this can be expected behavior when the loop times are not synchronized.
F144+n:24	73749 +512 x n	E1_08212 +512 x n	DWORD	%MD144+n.24	DWORD	Read/Write	Channel 1 Mode Bits 0-3 - Channel Mode 0 = Quadrature Axis Input 1 = SSI Axis Input 2 = SSI Register Input 3 = SSI Output Bit 4 - SSI Master/Slave [Applies only to SSI Output and SSI Register Input modes] 0 = Master - Clock is an output 1 = Slave - Clock is an input
F144+n:25	73751 +512 x n	E1_08214 +512 x n	DWORD	%MD144+n.25	DWORD	Read/Write	Channel 1 SSI Options Applies only to SSI Output and SSI Register Input modes] Bit 0-5 - SSI Data Bits Range: 8-32 Bit 6 - SSI Encoding 0=Binary, 1=Gray Code Bit 7 - Echo channel 0 SSI Input [Applies only to SSI Output modes on channel 1.] Bit 8 - Terminate Inputs [Applies to all SSI Output and SSI Register Input modes except SSI Output - Master.] SSI Register Input - Standard: Data Inputs SSI Register Input - Monitor: Clock/Data Inputs SSI Output - Slave: Clock Inputs Bit 16-31 - SSI Clock Rate (kHz) Specifies the clock rate in kHz. The actual rate will be determined by the available integer divisor (16500/SSIClockRatekHz-1). Initial supported values are 250, 500, and 971, with the default of 250 kHz.
F144+n:26	73753 +512 x n	E1_08216 +512 x n	DINT	%MD144+n.26	DINT	Read/Write	Channel 1 Wire Delay [Applies only to SSI Register Input modes] Time to delay (ns) from Clock to Data. This value will be converted to the nearest time delay that can be represented with [1..8] * [0..31] / 33MHz.
F144+n:27	73755 +512 x n	E1_08218 +512 x n	DWORD	%MD144+n.27	DWORD	Read/Write	Channel 1 Source/Dest [Applies only to SSI Output and SSI Register Input modes] For SSI Output mode, this is the address of the register to send out the SSI Output. Ignored if Echo is enabled. For SSI Register Input, this is the address of the register to save the value coming in on the SSI input.
F144+n:28	73757 +512 x n	E1_08220 +512 x n	DWORD	%MD144+n.28	DWORD	Read Only	Channel 1 SSI Status [Applies only to SSI Output and SSI Register Input modes] Bit 0 - Clock Wire Fault Wire Break for Clock inputs, Short for Clock outputs. Bit 1 - Data Wire Fault Wire Break for Data inputs, Short for Data outputs. Bit 2 - No Master Detected - Two or more loops (SSI Slave modes only) No master device is clocking SSI data--two or more loops in a row. Bit 3 - No Slave Detected (SSI Register Input only) Transducer or RMC not responding with data. Bit 4 - No Master Detected - One or more loops (SSI Slave modes only) This status register indicates that no clocked data was detected this loop time, even if this is the first loop this occurred. Notice that this can be expected behavior when the loop times are not synchronized.